Description
The high cost of prototyping at advanced technology nodes, as well as the complexity of future detectors, necessitate the use of a system design technique widely used in industry: design space exploration through high-level architecture studies to establish
precise and optimal requirements. This work presents Pix-ESL: a programmable SystemC framework for simulating the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, comprises an event generator and
connects with real-world physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy. This contribution outlines the framework's structure as well as a case study based on Velopix2.
Primary author
Jashandeep Dhaliwal
(CERN)
