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Description
Thermal processing of germanium-based architectures is essential for optoelectronic devices, yet surface and interfacial instabilities remain poorly understood [1-2]. A major drawback of these thermal processes is the formation of microscopic surface defects, specifically crystallographic pits or voids on Ge (100) surfaces. These irregularities, which vary based on annealing duration and preparation protocols, can compromise the structural integrity and uniformity of the thin films being deposited [4,5].
This work reports morphological and electrical studies of three Ge-based materials' stacks (Ge, Ge/ITO, and Ge/SiO2 /ITO) following thermal treatments at varying temperatures and under different atmospheric conditions.
For the study, n- and p-type Ge <100> wafers of 1-10 ohm*cm are used as reference, followed by the ITO and the SiO2/ITO deposition via RF Magnetron Sputtering. Annealing was performed at temperatures ranging from 200°C to 650°C, comparing a low vacuum environment (0.1 Pa Ar atmosphere) against a 1E5 Pa N2 atmosphere.
Morphological analysis via SEM and TEM revealed spontaneous pit formation in the Ge and Ge/ITO samples annealed in the Ar environment, even at relatively low temperatures. In the Ge reference, pit exhibit a pyramidal shape exposing <111> facets, consistent with surface free energy minimisation. Pit density increases with the temperature, while the average size does not change significantly. The void formation is tentatively attributed to the desorption of volatile GeO, possibly generated by interfacial reaction between Ge substrate and native oxide (GeO2) [3]. Conversely, Ge/ITO samples show pit formation localized at the ITO grain boundaries, with size scaling with the temperature. A different result is obtained for the Ge/SiO2/ITO stack, which remains completely defect-free under the same conditions. Furthermore, comparative tests show that annealing in a 1E5 Pa N2 atmosphere suppresses the pit formation across all the three systems.
Finally, electrical characterization indicates that this defect nucleation directly correlates with changes in electrical properties, specifically altering the sheet resistance.
Understanding these thermally driven morphological changes provides a critical framework for optimizing stable, defect-free germanium interfaces required for next-generation optoelectronic applications.
[1] C. Claeys, E. Simoen, Germanium-Based Technologies: From Materials to Devices, Elsevier, Amsterdam, 2007.
[2] L. Liyu, and X. Wang. "Germanium/Silicon Single Photon Avalanche Diodes for SWIR Applications: A Review." in IEEE Sensors Journal 25-13, (2025); pp. 23499 - 23513.
[3] Wang, S.-K. (2022). Kinetic Studies in GeO2/Ge System: A Retrospective from 2021 (1st ed.).
[4] L. Persichetti et al. "Formation of extended thermal etch pits on annealed Ge wafers", in Applied Surface Science, 462 (2018); pp. 86-94.
[5] P. Paphawee, and S. Kanjanachuchai. "Morphologies of Ge (100) surface annealed in nitrogen, forming gas, and vacuum", in Surfaces and Interfaces, 66 (2025); 106523.